TY - GEN
T1 - Dynamic partial reconfiguration manager
AU - Tarrillo, Jimmy
AU - Escobar, Fernando A.
AU - Kastensmidt, Fernanda Lima
AU - Valderrama, Carlos
PY - 2014
Y1 - 2014
N2 - Dynamic partial reconfiguration (DPR) is a technique that optimizes resource utilization of SRAM-based FPGAs, since it allows changing, on the fly, the functionality of a portion of its logic. A common DPR development flow requires the use of, at least, a microprocessor and several development tools (EDK, XSDK, PlanAhead); moreover, proposals are mainly based on MicroBlaze, ARM or PowerPC embedded processors, which also require extra memory control blocks. This article presents a generic DPR manager IP core (Intellectual Property), whose versatility allows the use of either any embedded processor or simple control logic. Results in terms of reconfiguration time and resources for Virtex 5 and Virtex 6 SRAM-FPGAs show its advantages and interest over traditional solutions.
AB - Dynamic partial reconfiguration (DPR) is a technique that optimizes resource utilization of SRAM-based FPGAs, since it allows changing, on the fly, the functionality of a portion of its logic. A common DPR development flow requires the use of, at least, a microprocessor and several development tools (EDK, XSDK, PlanAhead); moreover, proposals are mainly based on MicroBlaze, ARM or PowerPC embedded processors, which also require extra memory control blocks. This article presents a generic DPR manager IP core (Intellectual Property), whose versatility allows the use of either any embedded processor or simple control logic. Results in terms of reconfiguration time and resources for Virtex 5 and Virtex 6 SRAM-FPGAs show its advantages and interest over traditional solutions.
KW - Dynamic Partial Reconfiguration
KW - ICAP
KW - SRAM-FPGA
UR - http://www.scopus.com/inward/record.url?scp=84904562966&partnerID=8YFLogxK
U2 - 10.1109/LASCAS.2014.6820293
DO - 10.1109/LASCAS.2014.6820293
M3 - Conference contribution
AN - SCOPUS:84904562966
SN - 9781479925070
T3 - 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings
BT - 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings
PB - IEEE Computer Society
T2 - 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014
Y2 - 25 February 2014 through 28 February 2014
ER -