TY - GEN
T1 - Voice Recognition Acquisition and Storage System using VHDL and the DE1-SoC FPGA
AU - Arellanos, Elmer
AU - Remigio, Luis Dominguez
AU - Marquez, Jose Luis Ostos
AU - Nunez, Moises
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - This paper presents the design of a voice acqui-sition and recognition system in VHDL, mainly optimized for FPGA DE1-SoC. The system implements advanced digital signal processing techniques combined with classification through the K-Nearest Neighbors (KNN) algorithm. The system operates at a 320 kHz sampling rate, with a latency of 10 ns and power consumption of 1.2 W. The design enhances precision and noise rejection through the use of Hamming windows and integer-based processing. Future improvements will focus on the implementation of neural networks to replace the KNN algorithm and further increase system accuracy.
AB - This paper presents the design of a voice acqui-sition and recognition system in VHDL, mainly optimized for FPGA DE1-SoC. The system implements advanced digital signal processing techniques combined with classification through the K-Nearest Neighbors (KNN) algorithm. The system operates at a 320 kHz sampling rate, with a latency of 10 ns and power consumption of 1.2 W. The design enhances precision and noise rejection through the use of Hamming windows and integer-based processing. Future improvements will focus on the implementation of neural networks to replace the KNN algorithm and further increase system accuracy.
KW - DE1-SoC
KW - Digital Signal Processing
KW - FPGA
KW - K-Nearest Neighbors (KNN)
KW - VHDL
KW - Voice Recognition
UR - https://www.scopus.com/pages/publications/85217212526
U2 - 10.1109/INTERCON63140.2024.10833462
DO - 10.1109/INTERCON63140.2024.10833462
M3 - Conference contribution
AN - SCOPUS:85217212526
T3 - Proceedings of the 2024 IEEE 31st International Conference on Electronics, Electrical Engineering and Computing, INTERCON 2024
BT - Proceedings of the 2024 IEEE 31st International Conference on Electronics, Electrical Engineering and Computing, INTERCON 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 31st IEEE International Conference on Electronics, Electrical Engineering and Computing, INTERCON 2024
Y2 - 6 November 2024 through 8 November 2024
ER -