TY - GEN
T1 - Property specification and Static Verification of UML models
AU - Siveroni, Igor
AU - Zisman, Andrea
AU - Spanoudakis, George
PY - 2008
Y1 - 2008
N2 - We present a Static Verification Tool (SVT), a system that performs static verification on UML models composed of UML class and state machine diagrams. Additionally, the SVT allows the user to add extra behavior specification in the form of guards and effects by defining a small action language. UML models are checked against properties written in a special-purpose property language that allows the user to specify linear temporal logic formulas that explicitly reason about UML components. Thus, the SVT provides a strong foundation for the design of reliable systems and a step towards model-driven security
AB - We present a Static Verification Tool (SVT), a system that performs static verification on UML models composed of UML class and state machine diagrams. Additionally, the SVT allows the user to add extra behavior specification in the form of guards and effects by defining a small action language. UML models are checked against properties written in a special-purpose property language that allows the user to specify linear temporal logic formulas that explicitly reason about UML components. Thus, the SVT provides a strong foundation for the design of reliable systems and a step towards model-driven security
UR - https://www.scopus.com/pages/publications/49049084273
U2 - 10.1109/ARES.2008.194
DO - 10.1109/ARES.2008.194
M3 - Conference contribution
AN - SCOPUS:49049084273
SN - 0769531024
SN - 9780769531021
T3 - ARES 2008 - 3rd International Conference on Availability, Security, and Reliability, Proceedings
SP - 96
EP - 103
BT - ARES 2008 - 3rd International Conference on Availability, Security, and Reliability, Proceedings
PB - IEEE Computer Society
T2 - 3rd International Conference on Availability, Security, and Reliability, ARES 2008
Y2 - 4 March 2008 through 7 March 2008
ER -