Intra-chip traffic generation under autoregressive models based on time series obtained by TLM simulation

In the design flow of multi-processing system-on-chips (MPSoCs), the evaluation of communications structures, particularly, networks on chip (NoCs), plays a very important role, since it may show relevant characteristics on performance, energy consumption or cost. Simulation under a number of stimulus given by a traffic generator is a relevant solution for MPSoCs performance analysis. Traditional synthetic trace generators based on Poisson and classic Markovian models are not able to maintain the characteristics of an original application trace, such as burstiness or self-similarity. After Long Range Dependence characteristics had been found in intra-chip traffic, several approaches on the modeling of this kind of traffic were proposed, but restricted to the use of data obtained at RTL. In this work we present a methodology based on a fast hardware simulation at TLM to generate synthetic intra-chip traffic. The methodology encompasses the capture of the real data traffic, evaluation of the time series to determine the presence of Short or Long Range Dependence, time series fitting to the autoregressive moving-average (ARMA) or autoregressive fractionally integrated moving-average (ARFIMA) models, and the implementation of such models as a traffic generator.