Estimating power consumption of multiple modular redundant designs in SRAM-based FPGAs for high dependable applications

Triple Modular redundancy technique is mostly used to mask transient faults in circuits operating in dependable systems. The generalization of this technique (known as nMR) allows the use of more than three redundant copies of the circuit to increase the reliability under multiple faults. The main drawback of nMR is its high power consumption, which usually implies in n times the power consumption of a single circuit. In this work, we show that such affirmation is far for being true in case of embedding the entire redundant system into a single SRAM-based FPGA. We estimate power consumption in some case-study circuits protected by nMR in SRAM-based FPGAs and compare to a proposed model that estimates power consumption penalty. Results demonstrate that nMR can be implemented with low power overhead in FPGAs and therefore it is a suitable technique for most applications synthesized into this type of programmable devices that need to cope with massive multiple faults.