Dynamic partial reconfiguration manager

Jimmy Tarrillo; Fernando A. Escobar; Fernanda Lima Kastensmidt; Carlos Valderrama

doi:10.1109/LASCAS.2014.6820293

Dynamic partial reconfiguration manager

Jimmy Tarrillo, Fernando A. Escobar, Fernanda Lima Kastensmidt, Carlos Valderrama

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

15 Scopus citations

Abstract

Dynamic partial reconfiguration (DPR) is a technique that optimizes resource utilization of SRAM-based FPGAs, since it allows changing, on the fly, the functionality of a portion of its logic. A common DPR development flow requires the use of, at least, a microprocessor and several development tools (EDK, XSDK, PlanAhead); moreover, proposals are mainly based on MicroBlaze, ARM or PowerPC embedded processors, which also require extra memory control blocks. This article presents a generic DPR manager IP core (Intellectual Property), whose versatility allows the use of either any embedded processor or simple control logic. Results in terms of reconfiguration time and resources for Virtex 5 and Virtex 6 SRAM-FPGAs show its advantages and interest over traditional solutions.

Original language	English
Title of host publication	2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings
Publisher	IEEE Computer Society
ISBN (Print)	9781479925070
DOIs	https://doi.org/10.1109/LASCAS.2014.6820293
State	Published - 2014
Externally published	Yes
Event	2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Santiago, Chile Duration: 25 Feb 2014 → 28 Feb 2014

Publication series

Name	2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings

Conference

Conference	2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014
Country/Territory	Chile
City	Santiago
Period	25/02/14 → 28/02/14

Keywords

Dynamic Partial Reconfiguration
ICAP
SRAM-FPGA

Access to Document

10.1109/LASCAS.2014.6820293

Cite this

Tarrillo, J., Escobar, F. A., Kastensmidt, F. L., & Valderrama, C. (2014). Dynamic partial reconfiguration manager. In 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings Article 6820293 (2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings). IEEE Computer Society. https://doi.org/10.1109/LASCAS.2014.6820293

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title = "Dynamic partial reconfiguration manager",

abstract = "Dynamic partial reconfiguration (DPR) is a technique that optimizes resource utilization of SRAM-based FPGAs, since it allows changing, on the fly, the functionality of a portion of its logic. A common DPR development flow requires the use of, at least, a microprocessor and several development tools (EDK, XSDK, PlanAhead); moreover, proposals are mainly based on MicroBlaze, ARM or PowerPC embedded processors, which also require extra memory control blocks. This article presents a generic DPR manager IP core (Intellectual Property), whose versatility allows the use of either any embedded processor or simple control logic. Results in terms of reconfiguration time and resources for Virtex 5 and Virtex 6 SRAM-FPGAs show its advantages and interest over traditional solutions.",

keywords = "Dynamic Partial Reconfiguration, ICAP, SRAM-FPGA",

author = "Jimmy Tarrillo and Escobar, {Fernando A.} and Kastensmidt, {Fernanda Lima} and Carlos Valderrama",

year = "2014",

doi = "10.1109/LASCAS.2014.6820293",

language = "English",

isbn = "9781479925070",

series = "2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings",

publisher = "IEEE Computer Society",

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note = "2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 ; Conference date: 25-02-2014 Through 28-02-2014",

}

Tarrillo, J, Escobar, FA, Kastensmidt, FL & Valderrama, C 2014, Dynamic partial reconfiguration manager. in 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings., 6820293, 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings, IEEE Computer Society, 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014, Santiago, Chile, 25/02/14. https://doi.org/10.1109/LASCAS.2014.6820293

Dynamic partial reconfiguration manager. / Tarrillo, Jimmy; Escobar, Fernando A.; Kastensmidt, Fernanda Lima et al.
2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings. IEEE Computer Society, 2014. 6820293 (2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - Dynamic partial reconfiguration (DPR) is a technique that optimizes resource utilization of SRAM-based FPGAs, since it allows changing, on the fly, the functionality of a portion of its logic. A common DPR development flow requires the use of, at least, a microprocessor and several development tools (EDK, XSDK, PlanAhead); moreover, proposals are mainly based on MicroBlaze, ARM or PowerPC embedded processors, which also require extra memory control blocks. This article presents a generic DPR manager IP core (Intellectual Property), whose versatility allows the use of either any embedded processor or simple control logic. Results in terms of reconfiguration time and resources for Virtex 5 and Virtex 6 SRAM-FPGAs show its advantages and interest over traditional solutions.

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Tarrillo J, Escobar FA, Kastensmidt FL, Valderrama C. Dynamic partial reconfiguration manager. In 2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings. IEEE Computer Society. 2014. 6820293. (2014 IEEE 5th Latin American Symposium on Circuits and Systems, LASCAS 2014 - Conference Proceedings). doi: 10.1109/LASCAS.2014.6820293

Dynamic partial reconfiguration manager

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